The present invention relates to arrays for performing logic functions and, more particularly, it relates to a new decoder for PLAs.
Performing logic in an array of identical circuit elements each located at a unique intersection of an input and output line in a grid of input and output lines is well known. Co-pending application Ser. No. 537,219 filed on Dec. 30, 1974, Ser. No. 537,218, filed on Dec. 30, 1974; and Ser. No. 591,208, filed June 27, 1975 describe such a PLA in which a number of two-bit decoders feed inputs to a first array called a product term generator or an AND array which in turn supplies outputs to a second array called the sum of product term generator or an OR array. The input lines of these arrays can each have input variables fed to either or both ends. When input variables are fed to both ends of an input line the input line is segmented to separate logic functions performed on an input variable fed to one end from logic functions performed on input variables fed to the other end. The input variables fed to the input lines of the array are the four variables generated as the outputs of a two bit decoder. This permits the use of the four lines to perform logic functions involving two sets of variables where each set is made up of two variables fed to the same side of the array. Sometimes it is desirable that logic functions be performed on inputs of a single variable or that logic functions be performed on a set of two variables arranged on opposite sides of the array. This is not possible with the two-bit decoders now being used.